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rev1.3, nov. 2005 cms6416lax-75xx 64m(4mx16) low power sdram revision 1.3 november, 2005
rev1.3, nov. 2005 cms6416lax-75xx document title 64m(4mx16) low power sdram revision history final nov. 1 st , 2005 add h(pb-free & halogen free) descriptions 1.3 feb, 2005 change i dd 3p specification 1.2 jan.10 th , 2005 change setup/hold time 1.1 preliminary dec.6 th , 2004 change idd specifications 0.4 preliminary oct.20 th , 2004 extend vddmax limit for 2.5v product 0.3 preliminary jan.5 th , 2005 add pb & halogen free package item change from manual tcsr to auto tcsr change idd2n specifications 1.0 preliminary oct.6 th , 2004 add commercial & extended temperature options add package dimension 0.2 preliminary aug.13 th , 2004 correct typo. add write burst mode description 0.1 preliminary jun.25 th , 2004 initial draft 0.0 remark draft date history revision no.
rev1.3, nov. 2005 cms6416lax-75xx features - functionality - standard sdram functionality - programmable burst lengths : 1, 2, 4, 8, or full page - jedec compatibility - low power features - low voltage power supply : 2.5v/3.0v - auto tcsr(temperature compensated self refresh) - partial array self refresh power-saving mode - deep power down mode - driver strength control - operating temperature ranges: - special (-10 to +60 ) - commercial (0 to +70 ) - extended (-25 to +85 ) - industrial (-40 to +85 ) - lvcmos compatible io interface - 54ball fbga with 0.8mm ball pitch - CMS6416LAF : normal - cms6416lag : pb-free - cms6416lah : pb-free & halogen free functional description the cms6416lax-xxxx family is high-performance cmos dynamic rams (dram) organized as 4m x 16. these devices feature advanced circuit design to provide ultra-low active current and extremely low standby current.this is ideal for providing more battery life in portable applications such as wireless handsets. the device is compatible with the jedec standard lp-sdram specifications. selection guide 20ns 20ns 7.5ns 100mhz 18ns 18ns 6ns 133mhz 1.65-v dd 2.3-3.3v cms6416lax-75xx t rcd cl=2 access time(t ac ) cl=3 v ddq v dd t rp frequency voltage device column decoder column decoder column decoder bank 0 row addr latch/ decoder bank 3 bank 2 bank 1 bank 0 row addr latch/ decoder bank 0 memory array 4kx4k sense amp row add mux write drivers dqm mask read data latch data output reg column address latch bank control logic refresh counter addr reg data output reg ldqm - udqm dq0 - dq15 column decoder enhanced mode reg mode reg control logic cke clk /cs /we /cas /ras a0-a11 ba0-ba1 logic block diagram
rev1.3, nov. 2005 cms6416lax-75xx pin configuration for x16 v ss dq15 v ssq v ddq dq0 v dd dq13 v ddq v ssq dq2 dq1 dq14 dq11 v ssq v ddq dq4 dq3 dq12 dq9 v ddq v ssq dq6 dq5 dq10 nc v ss v dd ldqm dq7 dq8 clk cke /cas /ras /we udqm a 11 a 9 ba 0 ba 1 /cs nc a 7 a 6 a 0 a 1 a 10 a 8 a 5 a 4 a 3 a 2 v dd v ss 54 ball fbga(8mm x 8mm) 1 2 3 4 5 6 7 8 9 a b c d e f g h j
rev1.3, nov. 2005 cms6416lax-75xx pin description data input/output : data bus i/o dq no connect - nc dq power: provide isolated power to dqs for improved noise immunity. supply v ddq dq ground: provide isolated ground to dqs for improved noise immunity. supply v ssq power supply: voltage dependent on option. supply v dd ground. supply v ss address inputs: a0?a11 are sampled during the active command (row-address a0?a11) and read/write command (column-address a0?a7; with a10 defining auto precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine if all banks are to be precharged (a10 high) or bank selected by ba0, ba1 (a10 low). the address inputs also provide the op-code during a load mode register command. input a0-a11 input/output mask: l(u)dqm is sampled high and is an input mask signal for write accesses and an output enable signal for read accesses. input data is masked during a write cycle. the output buffers are placed in a high-z state (two-clock latency) when during a read cycle. ldqm corresponds to dq0 ? dq7 and udqm corresponds to dq8?dq15. input ldqm, udqm bank address input(s): ba0 and ba1 define to which bank the active, read, write or precharge command is being applied. these pins also provide the op-code during a load mode register command. input ba0, ba1 input input input input type /cas, /ras, /we /cs cke clk symbol chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands are masked when /cs is registered high. /cs provides for external bank selection on systems with multiple banks. /cs is considered part of the command code. command inputs : /cas, /ras, and /we (along with /cs) define the command being entered. clock enable: cke activates(high) and deactivates(low) the clk signal. deactivating the clock provides precharge power-down and se lf refresh operation(all banks idle), active power-down(row active in any bank) or clock suspend operation(burst/access in progress). cke is synchronous except after the device enters power-down and self refresh modes, where cke becomes asynchronous until af ter exiting the same mode. the input buffers, including clk, are disabled during power-down and self refresh modes, providing low standby power. cke may be tied high. clock : clk is driven by the system clock. a ll sdram input signals are sampled on the positive edge of clk. clk also increments the internal burst counter and controls the output registers. description
rev1.3, nov. 2005 cms6416lax-75xx functional description the fidelix 64mb sdram is a quad-bank dram that operates at 2.5v and includes a synchronous inter- face (all signals are registered on the positive edge of the clock signal, clk). each of the x16?s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. read and write accesses to the sdram are burst oriented; accesses start at a selected location and continue for a pro- grammed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write comm and. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0 and ba1 select the bank, a0- a11 select the row). the address bits (a0-a7) registered coincident with the read or write command are used to select the starting column location for the burst access.the sdram must be ini- tialized prior to normal operation. the following sections pro- vide detailed information regarding device initialization, register definition, command descriptions and device operation. initialization sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. once power is applied to v dd and v ddq (simultaneously) and the clock is stable (meets the clock specifications in the ac characteristics), the sdram requires a 100s delay prior to issuing any command other than a command inhibit or nop. the command inhibit or nop should be applied at least once during the 100s delay. after the 100s delay, a precharge command should be applied. all banks must then be precharged, thereby placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. after the auto refresh cycles are complete, the sdram is ready for mode register programming. because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. refer to figure 1.
rev1.3, nov. 2005 cms6416lax-75xx register definition there are two mode registers which contain settings to achieve low power consumption. the two registers : mode register and extended mode register are discussed below. mode register the mode register is used to define the specific mode of operation of the sdram. this definition includes the selec- tion of a burst length, a burst type, a cas latency, an operat- ing mode and a write burst mode, as shown in table 1. the mode register is programmed via the load mode regis- ter command and will retain the stored information until it is programmed again or the device loses power. mode register bits m0-m2 specify the burst length, m3 specifies the type of burst (sequential or interleaved), m4-m6 specify the cas latency, m7 and m8 specify the operating mode, m9 specifies the write burst mode, m10, m11, m12 and m13 should be set to zero.the mode register must be loaded when all banks are idle, and the controller must wait the specified time before ini- tiating the subsequent operation. violating either of these requirements will result in unspecified operation. burst length read and write accesses to the sdram are burst oriented. the burst length is programmable, as shown in table 2. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 1,2, 4, or 8 locations are available for both the figure 1. initialize and load mode register [1.2.3.] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 key key key raa hiz hiz clk cke /cs /ras /cas addr ba0 ba1 a10/ap dq /we dqm high level is necessary t rp t rc t rc precharge (all bank) auto refresh auto refresh normal mrs extended mrs row active a bank note : 1. the two auto refresh commands at t4 and t9 may be applied before either load mode register (lmr) command. 2. pre = precharge command, lmr = load mode register command, ar = auto refresh command, act = active command, ra = row addre ss, ba = bank address 3. the load mode register for both mr/emr and 2 auto refresh commands can be in any order; however, all must occur prior to an active command. ba1 ba0
rev1.3, nov. 2005 cms6416lax-75xx sequential and the interleaved burst types, and a full-page burst is available for the sequential type. the full-page burst is used in conjunction with the burst terminate command to gene- rate arbitrary burst lengths. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively select- ed. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1-a7 when the burst length is set to two; by a2-a7 when the burst length is set to four; and by a3-a7 when the burst length is set to eight. the remaining(least significant) address bit(s) is (are) used to select the starting location within the block. full-page bursts wrap within the page if the boundary is reached. burst type the burst type can be set to either sequential or interleaved by using the m3 bit in the mode register. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in table 2. [4.5.6.7.8.9.10.] cas latency m6-a6 m5-a5 m4-a4 bt m3-a3 burst length m2-a2 m1-a1 wb m9-a9 op mode m8-a8 m7-a7 reserved(set to ?0?) m0-a0 m10- a10 m11- a11 m12- ba0 m13- ba1 reserved reserved 1 0 1 reserved reserved 1 1 0 8 8 0 1 1 reserved reserved 1 0 0 2 2 0 0 1 4 4 0 1 0 reserved full page 1 1 1 1 1 0 0 0 m3=1 m3=0 burst length m2 m1 m0 reserved 1 1 1 reserved 1 0 1 reserved 1 1 0 3 0 1 1 reserved 1 0 0 1 0 0 1 2 0 1 0 reserved 0 0 0 cas latency m6 m5 m4 table 1. mode register definition. interleaved 1 sequential 0 burst type m3 prog. burst length 0 single mode access 1 write burst mode m9 - defined m6-m0 - 0 m7 all other states reserved - standard operation 0 operating mode m8 note : 4. for full-page accesses: y = 256 5. for a burst length of two, a1-a7 select the block-of-two burst; a0 selects the starting column within the block. 6. for a burst length of four, a2-a7 select the block-of-four burst; a0-a1 select the starting column within the block. 7. for a burst length of eight, a3-a7 select the block-of-eight burst; a0-a2 select the starting column within the block. 8. for a full-page burst, the full row is selected and a0-a7 select the starting column. 9. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 10. for a burst length of one, a0-a7 select the unique column to be accessed,and mode register bit m3 is ignored.
rev1.3, nov. 2005 cms6416lax-75xx 7-6-5-4-3-2-1-0 7-0-1-2-3-4-5-6 1 1 1 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 0 5-4-7-6-1-0-3-2 5-6-7-0-1-2-3-4 1 0 1 6-7-4-5-2-3-0-1 6-7-0-1-2-3-4-5 1 1 0 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7-0 0 0 1 2-3-0-1-6-7-4-5 2-3-4-5-6-7-0-1 0 1 0 3-2-1-0-7-6-5-4 3-4-5-6-7-0-1-2 0 1 1 3-2-1-0 3-0-1-2 1 1 a2 a1 a0 8 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 0 0-1-2-3 0-1-2-3 0 0 1-0-3-2 1-2-3-0 0 1 2-3-0-1 2-3-0-1 1 0 0-1 0-1 0 1-0 1-0 1 a1 a0 4 not supported bn, bn+1, bn+2?..bn,? n=a0-a8(location 0-y) full page(y) a0 2 type=interleaved type=sequential order of accesses within a burst starting column address burst length table 2. burst length definition. operating mode the normal operating mode is selected by setting m7 and m8 to zero; the other combinations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to both read and write bursts.test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first piece of output data. the latency can be set to one, two, or three clocks. if a read command is registered at clock edge r , and the latency is q clocks, the data will be available by clock edge r + q . the dqs will start driving as a result of the clock edge one cycle earlier (r + q- 1) , and provided that the relevant access times are met, the data will be valid by clock edge r + q. for example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at t0 and the latency is programmed to two clocks, the dqs will start driving after t1 and the data will be valid by t2, as shown in figure 2. reserved states should not be used as unknown operation or incompatibility with future versions may result. write burst mode when m9=0, the burst length programmed via m0-m2 applies to both read and write bursts; when m9=1, the programmed burst length applies to read bursts, but write accesses are single-location (non-burst) accesses.
rev1.3, nov. 2005 cms6416lax-75xx figure 2. cas latency t0 t1 t2 clk command dq cas latency=1 t lz dout read nop t oh t ac t0 t1 t2 clk command dq cas latency=2 read nop t3 nop dout t lz t oh t0 t1 t2 clk command dq cas latency=3 dout read t3 t4 nop nop nop t ac t lz t oh t ac
rev1.3, nov. 2005 cms6416lax-75xx extended mode register the extended mode register controls additional functions such as the temperature compensated self refresh (tcsr) control, partial array self refresh (pasr), and output drive strength.the extended mode register is programmed via the mode register set command (ba1=1, ba0=0) and retains the stored information until it is programmed again or the device loses power. the extended mode register must be programmed with m8 through m11 set to ?0?. the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time initiating any subsequent operation. violating either of these requirements re sults in unspecified operation. auto temperature compensated self refresh every cell in the dram requires refreshing due to the capacitor losing its charge over time. the refresh rate is dependent on temperature. at higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often. in order to save power consumption, according to the temperature, mobile-sdram includes the internal temperature sensor and control units to control the self refresh cycle automatically. partial array self refresh the partial array self refresh (pasr) feature allows the controller to select the amount of memory that will be refreshed during self refresh. the refresh options are all banks (banks 0, 1, 2, and 3); two banks(banks 0 and 1 or 2 and 3 by m7); and one bank (bank 0 or 2 by m7). write and read commands occur to any bank selected during standard operation, but only the selected banks in pasr will be refreshed during self refresh. the data in banks 2 and 3 will be lost when the two bank option with m7=0 is used. similarly the data will be lost in banks 1, 2, and 3 when the one bank option with m7=0 is used down . driver strength control the driver strength feature allows one to reduce the drive strength of the i/o?s on the device during low frequency operation. this allows systems to reduce the noise associated with the i/o?s switching. 0 0 bank up/down all must be set to ?0? 0 driver strength em6- a6 em5- a5 em4- a4 em3- a3 pasr em2- a2 em1- a1 em9- a9 em8- a8 em7- a7 1 em0- a0 em10- a10 em11- a11 em12- ba0 em13- ba1 table 4. extended mode register definition
rev1.3, nov. 2005 cms6416lax-75xx h x cke 1 0 a7 four banks 0 0 0 rfu x x 1 one bank (bank2) 0 1 0 rfu 1 1 0 rfu x x 1 one bank (bank 0) 0 1 0 rfu 1 1 0 two banks (bank2 & 3) 1 0 0 two banks (bank0 & 1) four banks self refresh coverage 0 a0 1 0 0 0 0 a1 a2 table 5. extended mode register table [11.12.] . x x x h l l l auto refresh or self refresh(enter self refresh mode) ) [18. 19.] x opcode x l l l l load mode register) [14.] active - l - - - - write enable/output enable) [20.] x bank/ col l/h h l h l read(select bank and column, and start read burst) [16.] valid bank/ col l/h l l h l write(select bank and column, and start write burst) [16.] active x x l h h l burst terminate x code x l h l l precharge(deactivate row in bank or banks) [17.] - h h x /we h x x x dqm bank/ row x x addr high z x x x dq h l l active(select bank and activate row) [15.] - - - write inhibit/output high-z) [20.] h x /cas command inhibit(nop) /ras h l no operation(nop) h x /cs name(function) table 6. commands [13.14.15.16.17.18.19.20.] . 1 0 1 0 a5 50% 1 25% 1 0 75% 0 100% driver strength a6 x x x l h h l deep power down(enter dpd mode) h h h h h h h h h l note : 11. em13 and em12 (ba1 and ba0) must be ?1, 0? to select the extended mode register(vs. the base mode register). 12. rfu: reserved for future use
rev1.3, nov. 2005 cms6416lax-75xx note : 13. cke is high for all commands shown except self refresh. 14. a0-a10 define the op-code written to the mode register. 15. a0-a11 provide row address, and ba0, ba1 determine which bank is made active. 16. a0-a7 provide column address; a10 high enables the auto precharge feature (nonpersistent), while a10 low disables the aut o precharge feature; ba0, ba1 determine which bank is being read from or written to. 17. a10 low: ba0, ba1 determine the bank being precharged. a10 high: all banks precharged and ba0, ba1 are ?don?t care.? 18. this command is auto refresh if cke is high, self refresh if cke is low. 19. internal refresh counter controls row addressing; all inputs and i/os are ?don?t care? except for cke. 20. activates or deactivates the dqs during writes (zero-clock delay) and reads (two-clock delay). ldqm controls dq0-7 and udqm controls dq8-15. table 6. commands [13.14.15.16.17.18.19.20.] . commands table 6. provides a reference of all the commands available with the state of the control signals for executing a specific command. command inhibit the command inhibit function effectively deselects the sdram by preventing new commands from being executed by the sdram, regardless of whether the clk signal is enabled. operations already in progress are not affected. load mode register the mode register is loaded via inputs a0-a11, ba0, ba1. the load mode register and load extended mode register commands can only be issued when all banks are idle, and a subsequent executable command cannot be issued until t mrd is met. table 1. and table 4. provide the definition for the mode register and extended mode register. no operation (nop) the no operation (nop) command is used to perform a nop to an sdram which is selected (/cs is low). this pre- vents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. active the active command is used to activate a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a11 selects the row. this row remains active for accesses until a precharge command is issued to that bank. a precharge command must be iss ued before opening a different row in the same bank. read read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a7 selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst. if auto precharge is not selected, the row will remain open for subsequent accesses. read data appears on the dqs subject to the logic level on the dqm inputs two clocks earlier. if a given dqm signal was registered high, the corresponding dqs will be high-z two clocks later; if the dqm signal was registered low, the dqs will provide valid data. write the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a7 selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst. if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the dqs is written to the memory array subject to the dqm input logic level appearing coincident with the data. if a given dqm signal is registered low, the corresponding data will be written to memory; if the dqm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. precharge the precharge command is used to deactivate the active row in a particular bank or the active row in all banks. the bank(s) will be available for a subsequent row access a spec- ified time (t rp ) after the precharge command is issued. input a10 determines whether one or all banks are to be pre- charged, and in the case where only one bank is to be pre- charged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ?don?t care.? once a bank has been pre- charged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. auto precharge auto precharge is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. auto precharge thus performs the same precharge command described above , without requiring an explicit command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or write burst. auto precharge does not apply in the full page mode burst. auto precharge is nonpersistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. the user must not issue another command to the same bank until the precharge time (t rp ) is completed. burst terminate the burst terminate command is used to truncate either fixed-length or full-page bursts. the most recently registered read or write command prior to the burst terminate command will be truncated.
rev1.3, nov. 2005 cms6416lax-75xx self refresh the self refresh command can be used to retain data in the sdram(without external clocking), even if the rest of the system is powered down. the self refresh command is initiated like an auto refresh command except cke is disabled (low). once the self refresh command is reg- istered, all the inputs to the sdram become ?don?t care? with the exception of cke, which must remain low. once self refresh mode is engaged, the sdram provides its own internal clocking, causing it to perform its own auto refresh cycles. the sdram must remain in self refresh mode for a minimum period equal to t ras and may remain in self refresh mode for an indefinite period beyond that. the procedure for exiting self refresh requires a sequence of commands. first, clk must be stable (meet the clock specifications in the ac characteristics) prior to cke going back high. once cke is high, the sdram must have nop commands issued (a minimum of two clocks) for t xsr because time is required for the completion of any internal refresh in progress. upon exiting the self refresh mode, auto refresh commands must be issued every 15.625s or less as both self refresh and auto refresh utilize he row refresh counter. deep power down deep power down mode is an operating mode to achieve maximum power reduction by cutting the power of the whole memory array of the device. data will not be retained once the device enters dpd mode. full initialization is required when the device exits from dpd mode. the dc value of dpd mode can?t be zero due to transistor?s leakage current; a reverse pn diode leakage current which is called ?junction leakage current? and a punch-through leakage current. [figure29.30] auto refresh auto refresh is used during normal operation of the sdram. this command is nonpersistent, so it must be issued each time a refresh is required. all active banks must be precharged prior to issuing an auto refresh command. the auto refresh command should not be issued until the minimum t rp has been met after the precharge command. the addressing is generated by the internal refresh controller. the address bits thus are a ?don?t care? during an auto refresh command. the fidelix 64mb sdram requires 4,096 auto refresh cycles every 64ms (t ref ), regardless of width option. providing a distributed auto refresh command every 15.625s will meet the refresh requirement and ensure that each row is refreshed. alternatively, 4,096 auto refresh commands can be issued in a burst at the minimum cycle rate (t rfc ), once every 64ms.
rev1.3, nov. 2005 cms6416lax-75xx absolute maximum ratings voltage on v dd /v ddq supply relative to v ss ?????????????.... ?1v to + 3.6v voltage on inputs, nc or i/o pins relative to v ss ??????????????. -1v to + 3.6v storage temperature(plastic) ????.??. -55 to + 150 power dissipation ?????????.?.??????1w *stresses greater than those listed under ?maximum ratings? may cause permanent damage to the device.this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to abso- lute maximum rating conditions for extended periods may affect reliability. operating range -10 to +60 special cms6416lax-75xs 0 to +70 commercial cms6416lax-75xc -25 to +85 extended cms6416lax-75xe 1.65v to v dd 2.3v to 3.3v -40 to +85 industrial cms6416lax-75xi v ddq v dd ambient temperature range device v 3.3 1.65 v ddq i/o supply voltage v 3.3 2.3 v dd supply voltage v 0.2 v ol data output low voltage : logic 0 : all inputs(0.1ma) ? 5 -5 ii input leakage current : any input 0v=v in =v dd (all other pins not under test=0v) v 0.3 -0.3 v il input low voltage : logic 0 all inputs [23.] v 0.9* v ddq v oh data output high voltage : logic 1 : all inputs(-0.1ma) v v ddq +0.3 0.8* v ddq v ih input high voltage : logic 1 all inputs [23.] ? 5 -5 l oz output leakage current : dqs are disabled ; 0v= v out =v ddq units max min symbol parameter / condition dc electrical characteristics and operating conditions [21,22] table 7. ac operating conditions [21.22.23.24.25.26.] v 0.5*v ddq input and output measurement reference level v 0.9* v ddq v ih input high voltage : logic 1 all inputs v 0.2 v il input low voltage : logic 0 all inputs units value symbol parameter / condition
rev1.3, nov. 2005 cms6416lax-75xx table 8. i dd specifications and conditions [21.22.26.27.] . note : 21. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (-40 c = ta = +85 c for it parts) is ensured. 22. an initial pause of 100s is required after power-up, followed by two auto refresh commands, before proper device operati on is ensured. (v dd and v ddq must be powered up simultaneously. v ss and v ssq must be at same potential.) the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 23. all states and sequences not shown are illegal or reserved. 24. in addition to meeting the transition rate specification, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 25. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 26. ac timing and i dd tests have v il and v ih , with timing referenced to v ih/2 = crossover point. if the input transition time is longer than t t (max), then the timing is referenced at v il (max) and v ih (min) and no longer at the v ih/2 crossover point. 27. i dd specifications are tested after the device is properly initialized. 28. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 29. the i dd current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 30. address transitions average one transition every two clocks. 31. other input signals are allowed to transition no more than once every two clocks and are otherwise at valid v ih or v il levels. 32. cke is high during refresh command period t rfc (min) else cke is low. the i dd 6 limit is actually a nominal value and does not result in a fail value t a =25 , f=1mhz, v dd(typ) test conditions pf pf units c in max 6 output capacitance c out input capacitance 4 description parameter capacitance ac test loads output z0=50 ? units -75 description parameter 10 200 250 350 62 40 16 3 12 300 35 ? operating current : burst mode ; continuo us burst ; read or write ; all banks active ; cas latency =3 [28.29.30.] i dd 4 ? active standby current in non power down mode ; cs#=high ; cke=high ; all banks active after t rcd met ; no access in progress [28.30.31.] i dd 3n ? auto refresh current : t rc =t rc (min) cas latency=3 ; cke,cs#=high [28.29.30.32.32.] i dd 5 ? self refresh current : cke <=0.2v, 4 banks i dd 6 ? self refresh current : cke <=0.2v, 2 banks ? self refresh current : cke <=0.2v, 1 banks ? deep power down i dd 7 ? precharge standby current in non ower down mode; cke=high ; all banks idle i dd 2n ? active standby current in power down mode ; cs#=high ; cke=low ; all banks active after t rcd met ; no access in progress [28.30.31.] i dd 3p ? ? i dd 1 precharge standby current in power down mode ; cke=low ; all banks idle i dd 2p operating current : active mode ; burst =1 ; read or write ; t rc = t rc (min); cas latency =3 [28.29.30.] 50 ? 30pf vddq/2
rev1.3, nov. 2005 cms6416lax-75xx ac characteristics 10 t clks2 ns 6 t hz (3) cl=3 ns 7.5 t hz (2) cl=2 ns 15 t rrd active banka to active bankb command ns 18 t rp precharge command period ns 70 t rfc auto refresh period ms 64 t ref refresh period(4096 rows) ns 18 t rcd active to read/write delay ns 70 t rc active to active command period ns 120000 45 t ras active to precharge command ns - t hz (1) cl=1 data high impedance time [25.] ns 1.0 t cmh /cs, /ras, /cas, /we, /dqm hold time to clock ns 2.0 t cms /cs, /ras, /cas, /we, /dqm setup time to clock ns 1.0 t cdh data in hold time to clock ns 2.0 t cds data in setup time to clock ns 2.5 t oh output hold time from clock ns - t ac (1) cl=1 ns 7.5 t ac (2) cl=2 ns 6 t ac (3) cl=3 clock access time t ck 1 t bdl last data-in to burst stop command [38.] t ck 2 t dpl data-in to precharge command [41.] ns t wr +t rp t dal data-in to active command [40.] t ck 0 t dwd write command to input data delay [38.] t ck 2 t dqz dqm to data high-impedance during reads [38.] t ck 0 t dqm dqm to data mask during writes [38.] t ck 0 t dqd dqm to input data delay [38.] t ck 1 t ped cke to clock enable or power-down exit setup mode [39.] t ck 1 t cked cke to clock disable or power-down entry mode [39.] t ck 1 t ccd read/write command to read/write command [38.] ns 80 t xsr exit self refresh to active command [37.] ns 15 t wr write recovery time [36.] t ck 2 t wr write recovery time [35.] ns 1.2 0.5 t t transition time [34.] ns 1.0 t ckh cke hold time to clock ns 2.0 t cks cke setup time to clock ns 1.0 t cah address hold time to clock ns 2.0 t cas address setup time to clock ns 2.5 t cl clock low time ns 2.5 t ch clock high time ns 7.5 t clks3 clock period [33.] max min parameter units -75 symbol ac characteristics
rev1.3, nov. 2005 cms6416lax-75xx ac characteristics t ck 1 t roh (1) cl=1 t ck 2 t roh (2) cl=2 t ck 3 t roh (3) cl=3 data-out to high-impedance from precharge command [40.] t ck 2 t mrd load mode register command to active or refresh command [42.] t ck 2 t rdl last data-in to precharge command [41.] t ck 1 t cdl last data-in to new read/write command [38.] max min parameter units -75 symbol ac characteristics note : 33. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (read, write, including t wr , and precharge commands). cke may be used to reduce the data rate. 34. ac characteristics assume t t = 1ns. 35. auto precharge mode only. 36. precharge mode only. 37. clk must be toggled a minimum of two times during this period. 38. required clocks are specified by jedec functionality and are not dependent on any timing parameter. 39. timing actually specified by t cks ; clock(s) specified as a reference only at minimum cycle rate. 40. timing actually specified by t wr plus t rp ; clock(s) specified as a reference only at minimum cycle rate. 41. timing actually specified by t wr . 42. jedec and pc100 specify three clocks.
rev1.3, nov. 2005 cms6416lax-75xx operation bank / row activation before any read or write commands can be issued to a bank within the sdram, a row in that bank must be ?opened? (activated). this is accomplished via the active command, which selects both the bank and the row to be activated. a read or write command may then be issued to that row, subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. for example, a t rcd specification of 20ns with a 125 mhz clock (8ns period) results in 2.5 clocks, rounded to 3. (the same procedure is used to convert other specification limits from time units to clock cycles.) a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (precharged). the minimum time interval between successive active commands to the same bank is defined by t rc . a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive active commands to different banks is defined by t t rrd . reads read bursts are initiated with a read command, as shown in figure 3. the starting column and bank addresses are provided with the read command, and auto precharge is either enabled or disabled for that burst access. for the generic read comm- ands used in the following illustrations, auto precharge is disab- led. during read bursts, the valid data-out element from the starting column address will be available following the cas latency after the read command. each subsequent data-out element will be valid by the next positive clock edge. figure 2. shows general timing for each possible cas latency setting. upon completion of a burst, assuming no other comm ands have been initiated, the dqs will go high-z. a fullpage burst will continue until terminated. (the burst will wrap around at the end of the page). a continuous flow of data can be maintained by having addtional read burst or single read command. the first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst that is being truncated. the new read command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 4. for cas latencies of one, two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. full-speed random read accesses can be performed to the same bank, as shown in figure 5. , or each subsequent read may be performed to a different bank. figure 3. read command clk cke /cs /ras /cas /we a0-a7 a9, a11 a10 ba0, 1 read command high column address bank address enable auto precharge disable auto precharge don?t care
rev1.3, nov. 2005 cms6416lax-75xx figure 4. consecutive burst reads -transition from burst of 4 read to a single read for cas latency 1,2,3 t0 t1 t2 cas latency=1 t3 t4 t5 clk command address dout n dout n+1 dout n+2 dout n+3 dout b read nop nop nop read nop bank col n bank col b x=0cycles dq t0 t1 t2 cas latency=2 t3 t4 t5 clk command address dout n dout n+1 dout n+2 dout n+3 dout b read nop nop nop read nop bank col n bank col b x=1cycles dq t6 nop
rev1.3, nov. 2005 cms6416lax-75xx figure 5. random read accesses for cas latency =1,2,3 figure 4. consecutive burst reads -transition from burst of 4 read to a single read for cas latency 1,2,3 t0 t1 t2 cas latency=3 t3 t4 t5 clk command address dout n dout n+1 dout n+2 dout n+3 dout b read nop nop nop read nop bank col n bank col b x=2cycles dq t6 nop t7 nop t0 t1 t2 cas latency=1 t3 t4 clk command address dout n dout a dout x dout m read read read read nop bank col n dq bank col a bank col x bank col m
rev1.3, nov. 2005 cms6416lax-75xx a read burst can be terminated by a subsequent write com- mand, and data from a fixed length read burst may be immediately followed by data from a write command (subject to bus turnaround limitations). the write burst may be initiated on the clock edge immediately following the last (or last desired) data element from the read burst, provided that i/o contention can be avoided. in a given system design, there may be a possibility that the device driving the input data will go low-z before the sdram dqs go high-z. in this case, at least a single-cycle delay should occur between the last read data and the write command. the dqm input is used to avoid i/o contention, as shown in figure 6. and figure 7. . the dqm signal must be asserted (high) at least two clocks prior to the write command (dqm latency is two clocks for output buffers) to suppress data-out from the read. once the write comma- nd is registered, the dqs will go high-z (or remain high-z), regardless of the state of the dqm signal, provided the dqm figure 5. random read accesses for cas latency =1,2,3 t0 t1 t2 cas latency=2 t3 t4 t5 clk command address dout n dout a dout x dout m read read read read nop nop bank col n dq t0 t1 t2 cas latency=3 t3 t4 t5 clk command address dout n dout a dout x dout m read read read read nop nop bank col n dq t6 nop bank col a bank col x bank col m bank col a bank col x bank col m
rev1.3, nov. 2005 cms6416lax-75xx was active on the clock just prior to the write command that truncated the read command. the dqm signal must be as- serted prior to the write command (dqm latency is zero clocks for input buffers) to ensure that the written data is not masked. figure 6. shows the case where the clock frequency allows for bus contention to be avoided without adding a nop cycle, and figure 7. shows the case where the additional nop is needed. figure 6. read to write t0 t1 t2 cas latency=3 t3 t4 clk command address dout n din b read nop nop nop write bank col n dq bank col b dqm t hz t ds t ck
rev1.3, nov. 2005 cms6416lax-75xx figure 8. read interrupted by write and dqm ; cas latency =2 t0 t1 t2 cas latency=3 t3 t4 clk command address dout n din b read nop nop nop nop bank col n dq dqm t hz t ds t5 write bank col b t ck clk cmd t0 t1 t2 t3 t4 t5 t6 t7 t8 read write read masked by write din n din n+1 din n+2 din n+3 read masked by dqm read write din n din n+1 din n+2 din n+3 read cas=2 read write din n din n+1 din n+2 din n+3 dout n dqm cmd dqm cmd dqm dq dq dq figure 7. read to write with extra clock cycle
rev1.3, nov. 2005 cms6416lax-75xx a fixed-length read burst or a full-page burst may be fol- lowed by, or truncated with, a precharge command to the same bank . the precharge command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 9. for each possible cas latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. following the precharge comman- d, a subsequent command to the same bank cannot be issued until t rp is met. note that part of the row precharge time is hidden during the access of the last data element(s). the burst terminate command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 10. for each possible cas latency; data element n + 3 is the last desired data element of a longer burst. figure 9. read to precharge t0 t1 t2 cas latency=1 t3 t4 t5 dout n dout n+1 dout n+2 dout n+3 read nop nop nop precharge nop bank a col n bank (a or all) x=0cycles t6 nop t7 active bank a row t rp t0 t1 t2 cas latency=2 t3 t4 t5 dout n dout n+1 dout n+2 dout n+3 read nop nop nop precharge nop bank a col n bank (a or all) x=1cycles t6 nop t7 active bank a row t rp clk command address dq clk command address dq
rev1.3, nov. 2005 cms6416lax-75xx figure 9. read to precharge figure 10. terminating a read burst t0 t1 t2 cas latency=3 t3 t4 t5 clk command address dout n dout n+1 dout n+2 dout n+3 read nop nop nop precharge nop bank a col n bank (a or all) x=2cycles dq t6 nop t7 active bank a row t rp t0 t1 t2 t3 t4 t5 dout n dout n+1 dout n+2 dout n+3 read nop nop nop burst terminate nop bank a col n x=0cycles t6 nop t7 nop cas latency=1 clk command address dq
rev1.3, nov. 2005 cms6416lax-75xx figure 10. terminating a read burst t0 t1 t2 cas latency=2 t3 t4 t5 clk command address dout n dout n+1 dout n+2 dout n+3 read nop nop nop burst terminate nop bank a col n x=1cycles dq t6 nop t7 nop t0 t1 t2 cas latency=3 t3 t4 t5 clk command address dout n dout n+1 dout n+2 dout n+3 read nop nop nop burst terminate nop bank a col n x=2cycles dq t6 nop t7 nop
rev1.3, nov. 2005 cms6416lax-75xx figure 11. read & write cycle at same bank @burst length=4, t dpl =2clk (100mhz) note : 45. minimum row cycle times is required to complete internal dram operation. 46. row precharge can interrupt burst on any cycle.[cas latency -1] number of valid output data is available after row precha rge. last valid output will be hi-z(t shz ) after the clock. 47. access time from row active command. t cc *(t rcd + cas latency - 1) + t sac 48. out put will be hi-z after the end of burst. (1,2,3,8 & full page bit burst) qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 don?t care 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high clock cke t rc *note 45. t rcd /cs /ras /cas raa caa rab cab addr ba0 ba1 rab raa a10/ap cl=2 t oh t sac t rac t shz *note 48. *note 47. t dpl qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 t oh t sac t rac t shz *note 48. *note 47. t dpl cl=3 /we dqm row active (a-bank) read (a-bank) precharge (a-bank) row active (a-bank) write (a-bank) precharge (a-bank) *note 46. dq t rp
rev1.3, nov. 2005 cms6416lax-75xx figure 12. read & write cycle at same bank @burst length=4, t dpl =2clk (133mhz) qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 don?t care 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high clock cke t rc *note 45. t rcd /cs /ras /cas raa caa rab cab addr ba0 ba1 rab raa a10/ap cl=2 t oh t sac t rac t shz *note 48. *note 47. t dpl qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 t oh t sac t rac t shz *note 48. *note 47. t dpl cl=3 /we dqm row active (a-bank) read (a-bank) precharge (a-bank) row active (a-bank) write (a-bank) *note 46. dq t rp
rev1.3, nov. 2005 cms6416lax-75xx figure 13. page read cycle at same bank @ burst length=4 write write bursts are initiated with a write command,as shown in figure 14. the starting column and bank addresses are provided with the write command, and auto precharge is note : 49. row precharge will interrupt writing. last data input, t dpl before row precharge, will be written. qaa0 qaa1 qaa2 qbb0 don?t care 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high clock cke /cs /ras /cas raa rbb cdd addr ba0 ba1 rdd raa a10/ap cl=2 cl=3 /we dqm row active (a-bank) read (a-bank) precharge (a-bank) precharge (d-bank) *note 49. caa rcc cbb rdd ccc rbb rcc qbb1 qbb2 qcc0 qcc1 qcc2 qdd0 qdd1 qdd2 qaa0 qaa1 qaa2 qbb0 qbb1 qbb2 qcc0 qcc1 qcc2 qdd0 qdd1 qdd2 dq row active (b-bank) row active (c-bank) read (b-bank) read (c-bank) precharge (b-bank) read (d-bank) precharge (c-bank)
rev1.3, nov. 2005 cms6416lax-75xx either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at the com- pletion of the burst. during write bursts, the first valid data-in element will be registered coincident with the write command. subsequent data elements will be registered on each successive positive clock edge. upon completion of a fixed- length burst, assuming no other commands have been initiated, the dqs will remain high-z and any additional input data will be ignored (see figure 15.). a fullpage burst w ill continue until terminated. (wrap around at the end of the page) an example is shown in figure 16. . data n + 1 is either the last of a burst of two or the last desired of a longer burst. a write command can be initiated on any clock cycle fol- lowing a previous write command. full-speed random write accesses within a page can be performed to the same bank, as shown in figure 17. , or each subsequent write may be performed to a different bank. figure 14. write command clk cke /cs /ras /cas /we a0-a7 a9, a11 a10 ba0, 1 write command high column address bank address enable auto precharge disable auto precharge don?t care
rev1.3, nov. 2005 cms6416lax-75xx data for a fixed-length write burst a full-page write burst may be followed by, or truncated with, a precharge com- mand to the same bank.the precharge command should be issued t wr after the clock edge at which the last desired input data element is registered. the auto precharge mode requires a t wr of at least one clock plus time, regardless of frequency. in addition, when truncating a write burst, the dqm signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the precharge command. an example is shown in figure 19. data n + 1 is either the last of a burst of two or the last desired of a longer burst. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. figure 16. write to write - transition fr om a burst of 2 to a single write figure 15. write burst - burst length of 2 t0 t1 t2 clk command address write nop t3 nop nop bank col n dq din n din n+1 t0 t1 t2 clk command address write nop write bank col n dq din n din n+1 bank col b din b
rev1.3, nov. 2005 cms6416lax-75xx figure 18. write to read burst of 2 write and read(cas latency =2) figure 17. random write cycles t0 t1 t2 clk command address write write t3 write write bank col n dq din n din a din x din m bank col a bank col x bank col m clk command address dq t0 t1 t2 write nop t3 read nop bank col n din n din n+1 bank col b t4 t5 nop nop dout b dout b+1
rev1.3, nov. 2005 cms6416lax-75xx figure 19. write to precharge fixed-length or full-page write bursts can be truncated with the burst terminate command. when truncating a write burst, the input data applied coinci dent with the burst terminate command will be ignored. the last data written (provided that dqm is low at that time) will be the input data applied one clock previous to the burst terminate t0 t1 t2 t3 t4 t5 write nop precharge nop active bank col n t6 nop din n din n+1 bank (a or all) bank a row t rp t wr t wr @t ck >=15ns t wr @t ck <=15ns write nop nop precharge nop nop bank col n active din n din n+1 bank (a or all) bank a row t rp t wr clk command address dq dqm command address dq dqm figure 20. terminating a write burst t0 t1 t2 clk command address write burst terminate next command bank col n dq din n (address) (data) nop
rev1.3, nov. 2005 cms6416lax-75xx command. this is shown in figure 20. , where data n is the last desired data element of a longer burst. precharge the precharge command (see figure 21. ) is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access some specified time (t rp ) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. when all banks are to be precharged, inputs ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. power-down power-down occurs if cke is registered low coincident with a nop or command inhibit when no accesses are in progress. if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and output buffers, excluding cke, for maximum power savings while in standby. the device may not remain in the power-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. the power-down state is exited by registering a nop or command inhibit and cke high at the desired clock edge(meeting t cks ). see figure 22. .
rev1.3, nov. 2005 cms6416lax-75xx figure 21. precharge command clk cke /cs /ras /cas /we a0-a9 a10 ba0, 1 precharge command high bank address all banks bank selected don?t care
rev1.3, nov. 2005 cms6416lax-75xx clock suspend the clock suspend mode occurs when a column access/ burst is in progress and cke is registered low. in the clock suspend mode, the internal clock is deactivated, ?freezing? the synchronous logic. for each positive clock edge on which cke is sampled low, the next internal positive clock edge is suspended. any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the dq pins remains driven; and burst- counters are not incremented, as long as the clock is sus- pended. (see examples in figure 23. and figure 24. .) clock suspend mode is exited by registering cke high; the internal clock and related operation will resume on the subsequent positive clock edge. burst read/single write in this mode, all write commands result in the access of a single column location (burst of one), regardless of the progra- mmed burst length. the burst read/single write mode is entered by programming the write burst mode bit (m9) in the mode register to a logic 1. read commands access columns according to the programmed burst length and sequence. figure 22. power down input buffers gated off clk command nop active cke >=t cks nop t cks all banks idle enter power down mode exit power down mode t rcd t ras t rc
rev1.3, nov. 2005 cms6416lax-75xx figure 23. clock suspen d during write burst t0 t1 t2 t3 t4 clk command address nop write nop dq cke t5 nop internal clk bank col n din n din n+1 din n+2
rev1.3, nov. 2005 cms6416lax-75xx dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered. (figure 26. ) write with auto precharge 3. interrupted by a read(with or without auto precharge): a read to bank m will interrupt a write on bank n when regis- tered , with the data-out appearing cas latency later. the pre- charge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write to bank n will be data-in registered one clock prior to the read to bank m.(figure 27. ) 4. interrupted by a write ( with or without auto precharge): a write to bank m will interrupt a write on bank n when registered. the precharge to bank n will begin after t wr is met ,where t wr begins when the write to bank m is registered. the latest valid data write to bank n will be data registered one clock prior to a write to bank m.( figure 28. ) figure 24. clock suspend during read burst - burst of 4 (cas latency =2) t0 t1 t2 t3 t4 clk command address read nop dq cke t5 nop internal clk bank col n dout n+1 dout n+2 t6 nop dout n+3 dout n nop nop concurrent auto precharge if an access command with auto precharge is being execeuted an access command (either a read or write ) is not allowed by sdram?s. if this feature is allowed then the sdram supports concurrent auto precharge. fidelix sdrams support concurrent auto precharge. four casees where concurrent auto precharge occurs are defined below. read with auto precharge 1.interrupted by a read(with or without auto precharge): a read to bank m will interrupt a read on bank n, cas latency later. the precharge to bank n will begin when the read to bank m is registered. (figure 25. ) 2. interrupted by a write(with or without auto precharge): a write to bank m will interrupt a read on bank n when registered.
rev1.3, nov. 2005 cms6416lax-75xx figure 26. read with auto precharge inte rrupted by a write(read cas latency =3) figure 25. read with auto precharge in terrupted by a read(cas latency =3) clk command address dq t0 t1 t2 cas latency=3(bank n) t3 t4 t5 din d din d+1 din d+2 din d+3 read-ap bank n nop nop nop t6 nop t7 nop interrupt burst, precharge idle page active write with burst of 4 write-bank bank n bank m bank n col a bank m col d page active read with a burst of 4 nop write-ap bank m internal states dqm dout a clk command address dq t0 t1 t2 cas latency=3(bank n) t3 t4 t5 dout a dout a+1 dout d dout d+1 nop read-ap bank n nop read-ap bank m nop nop t6 nop t7 nop interrupt burst, precharge idle page active read with burst of 4 pr echarge bank n bank m bank n col a bank m col d cas latency=3(bank m) page active read with a burst of 4 internal states t rp - bank n t rp - bank m t wr -bank m t rp - bank n
rev1.3, nov. 2005 cms6416lax-75xx figure 28. write with auto precharge interrupted by a write figure 27. write with auto precharge in terrupted by a read(cas latency =3) clk command address dq t0 t1 t2 cas latency=3(bank m) t3 t4 t5 din a din a+1 dout d dout d+1 nop write-ap bank n nop read-ap bank m nop nop t6 nop t7 nop interrupt burst, write-bank precharge page active read with burst of 4 pre charge bank n bank m bank n col a bank m col d page active write with a burst of 4 internal states t rp - bank n clk command address dq t0 t1 t2 t3 t4 t5 din a din a+1 nop write-ap bank n nop nop t6 nop t7 nop interrupt burst, write-bank precharge page active write with burst of 4 write-bank bank n bank m bank n col a bank m col d page active write with a burst of 4 internal states write-ap bank m nop t rp -bank m t wr -bank n t wr -bank m din a+2 din d din d+1 din d+2 din d+2 t wr - bank n t rp -bank n
rev1.3, nov. 2005 cms6416lax-75xx figure 29. deep power down mode entry figure 30. deep power down mode exit the deep power down mode is entered by having burst termination command, while cke is low. the deep power down mode has to be maintained for a minimum of 100us. the following diagram illustrates deep power down mode entry. deep power down mode entry the deep power down mode is exited by asserting cke high. after the exit, the following sequence is needed to enter a new command 1. maintain nop input conditions for a minimum of 200us 2. issue precharge commands for all banks of the device 3. issue 8 or more auto refresh commands 4. issue a mode register set command to initialize the mode register 5. issue a extended mode register set command to initialize the extended mode register the following timing diagram illustrates deep power down exit sequence deep power down mode exit sequence clk command nop precharge all bank nop burst terminate cke nop precharge if needed deep power down entry t rp clk command cke deep power down exit active address bank a row key key 200 us precharge all bank a10 aref precharge all bank nop emrs mrs nop nop normal mrs extended mrs row active a bank t rp
rev1.3, nov. 2005 cms6416lax-75xx power down entry command inhibit or nop all banks idle l h self refresh entry clock suspend entry auto refresh valid all banks idle reading or writing see table 10. h h maintain clock suspend x clock suspend exit power down exit self refresh command inhibit or nop command inhibit or nop power down [54.] self refresh [55.] h l exit clock suspend x clock suspend [56.] x x command n maintain self refresh maintain power down action n l current state self refresh l note : 50. cke n is the logic state of cke at clock edge n; cke n-1 was the state of cke at the previous clock edge. 51. current state is the state of the sdram immediatly prior to the clock edge n. 52. command n is the command registered at clock edge n , and action n is a result of command n . 53. all states and sequences not shown are illegal or reserved. 54. exiting power down at clock edge n will put the device in all the banks idle state in time for clock edge n+1(provided the t cks is met) 55. exiting self refresh at clock edge n will put the device in all the banks idle state once t xsr is met. command inhibit or nop commands should be issued on any clock edges occuring during the t xsr period. a minimum of two nop commands must be provided during the t xsr period. 56. after exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n+1. power down cke n cke n-1 table 9. cke [50.51.52.53.] . table 10. curent state bank n, command to bank n [57.58.59.60.61.62.] . l l h h h x we# load mode register [63.] l l l precharge [67.] h l l idle l l active (select and activate row) h l auto refresh [63.] l l l h x cas# no operation (nop/continue previous operation) command inhibit (nop/continue previous operation) command(action) any ras# h h x cs# current state note : 57. this table applies when cke n-1 was high and cke n is high (see table 9. ) and after t xsr has been met (if the previous state was self refresh). 58. this table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. exceptions are covered in the notes below. 59. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 60. the following states must not be interrupted by a command issued to the same bank. command inhibit or nop commands, or all owable commands to the other bank should be issued on any clock edge occurring during these states. allowable commands to the other bank are determined by its cu rrent state and table 10. and according to table 11. . precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank will be in the idle state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank will be in the row active state. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. write w/auto precharge enabled: starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. 61. the following states must not be interrupted by any executable command; command inhibit or nop commands must be applied on each positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rc is met. once t rc is met, the sdram will be in the all banks idle state. accessing mode register: starts with registration of a load mode register command and ends when t mrd has been met. once t mrd is met, the sdram will be in the all banks idle state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks will be in the idle state. 62. all states and sequences not shown are illegal or reserved. 63. not bank-specific; requires that all banks are idle. 64. may or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 65. not bank-specific; burst terminate affects the most recent read or write burst, regardless of bank. 66. reads or writes listed in the command (action) column include reads or writes with auto precharge enabled and reads or writes wi th auto precharge disabled. 67. does not affect the state of the bank and acts as a nop to that bank.
rev1.3, nov. 2005 cms6416lax-75xx table 10. curent state bank n, command to bank n [57.58.59.60.61.62.] . write (select column and start write burst) [66.] l l h l read (select column and start new read burst) [66.] h l h l read(auto precharge disabled) write (select column and start write burst) [66.] l l h l precharge (truncate read burst, start recharge) [64.] l h l l burst terminate [65.] l h h l l l l h l h we# precharge (truncate write burst, start precharge) [64.] h l l burst terminate [65.] h h l write (auto precharge disabled) l l read (select column and start read burst) [66.] l h write (select column and start new write burst) [66.] l h l h l cas# precharge (deactivate row in bank or banks) [64.] read (select column and start read burst) [66.] command(action) row active ras# l l h cs# current state table 11. current state bank n, command to bank m [68.69.70.71.72.73.] . active (select and activate row) h h l l read(auto precharge disabled) read (select column and start new read burst) [74.78.] h l h l write (select column and start write burst) [74.79.] l l h l precharge [76.] l h l l idle no operation (nop/continue previous operation) h h h l active (select and activate row) h h l l row activating, active, or precharging read (select column and start read burst) [74.] h l h l write (select column and start write burst) [74.] l l h l precharge l h l l l l h h x x we# write (select column and start new write burst) [76.80.] l h l precharge [76.] h l l write(auto precharge disabled) l x active (select and activate row) h l read (select column and start read burst) [74.79.] l h l x x cas# any command otherwise allowed to bank m command inhibit (nop/continue previous operation) command(action) any ras# x h x cs# current state
rev1.3, nov. 2005 cms6416lax-75xx table 11. current state bank n, command to bank m [68.69.70.71.72.73.] . active (select and activate row) l h l l read (with auto precharge) read (select column and start new read burst) [74.75.81.] h l h l write (select column and start write burst) [74.75.82.] l l h l precharge [76.] l h l l l l h h we# write (select column and start new write burst) [74.75.84.] l h l precharge [76.] h l l write (with auto precharge) l active (select and activate row) h l read (select column and start read burst) [74.75.83.] l h l cas# command(action) ras# cs# current state note : 68. this table applies when cke n-1 was high and cke n is high and after t xsr has been met (if the previous state was self refresh). 69. this table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). exceptions are covered in the notes below. 70. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled, and ends when t rp has been met. once t rp is met, the bank will be in the idle state. write w/auto precharge enabled: starts with registration of a write command with auto precharge enabled, and ends when t rp has been met. once t rp is met, the bank will be in the idle state. 71. auto refresh, self refresh and load mode register commands may only be issued when all banks are idle. 72. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 73. all states and sequences not shown are illegal or reserved. 74. reads or writes to bank m listed in the command (action) column include reads or writes with auto precharge enabled and reads or writes with auto precharge d isabled. 75. concurrent auto precharge: bank n will initiate the auto precharge command when its burst has been interrupted by bank m ?s burst. 76. burst in bank n continues as initiated. 77. for a read without auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the read on bank n , cas latency later. 78. for a read without auto precharge interrupted by a write (with or without auto precharge), the write to bank m will interrupt the read on bank n when registered. dqm should be used twwo clock prior to the write command to prevent bus contention. 79. for a write without auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the write on bank n when registered, with the data-out appearing cas latency later. the last valid write to bank n will be data-in registered one clock prior to the read to bank m . 80. for a write without auto precharge interrupted by a write (with or without auto precharge), the write to bank m will interrupt the write on bank n when registered. the last valid write to bank n will be data-in registered one clock prior to the read to bank m . 81. for a read with auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the read on bank n , cas latency later. the precharge to bank n will begin when the read to bank m is registered (figure 25.) . 82. for a read with auto precharge interrupted by a write (with or without auto precharge), the write to bank m will interrupt the read on bank n when registered. dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered (figure 26. ). 83. for a write with auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the write on bank n when registered, with the data-out appearing cas latency later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write to bank n will be data-in registered one clock prior to the read to bank m (figure 27. ). 84. for a write with auto precharge interrupted by a write (with or without auto precharge), the write to bank m will interrupt the write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered. the last valid write to bank n will be data registered one clock prior to the write to bank m (figure 28. ).
rev1.3, nov. 2005 cms6416lax-75xx package dimension 54 ball fine pitch bga (8 x 8 x 1.0 mm) top view bottom view side view unit : millimeters e d #a1 a1 index mark 9 8 7 6 5 4 3 2 1 e/2 d/2 e e1 d1 0.40 0.35 0.30 z 0.50 0.45 0.40 b - 0.80 - e - 6.40 - d1 - 8.00 - d - 6.40 - e1 - 8.00 - e 1.20 - - a max typ min - b e a z e a b c d e f g h j 1 2 3 4 5 6 7 8 9 a b c d e f g h j

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